Non-volatile memory (NVM) is a memory device that retains content stored therein even when power is removed. EEPROM and flash memory are two commonly used non-volatile memory devices. In particular, flash memory has become widely used in electronic devices, especially portable electronic devices, because of its ability to provide data storage at low power levels. Modern day flash memory devices are typically implemented using a floating gate MOS transistor device as the memory cells. A floating gate MOS transistor device includes a floating gate that is formed between a control gate and the channel region (the substrate) of the MOS device and at least partially vertically aligned with the control gate. Charge storage on the floating gate determines the stored data state (“0” or “1”) of the memory cell.
In a non-volatile memory cell implemented using a floating gate MOS device, programming of the memory cell, or writing data to the memory cell, is accomplished by transferring charge carriers from the semiconductor substrate (the source or the drain) to the floating gate by tunneling through the thin gate oxide layer. Typically, a block of non-volatile memory cells is first erased by applying bias conditions to remove the charges stored on the floating gate. Then, the non-volatile memory cells can be written or programmed, usually one byte or word at a time, by applying the bias conditions opposite to the erase operation. Erase and programming operation of non-volatile memory devices require a relatively large voltage and current.
A flash memory cell is read by applying a gate bias to the control gate and sensing the stored data state on the drain terminal of the flash memory cell, which is coupled to the bit-line of the memory array. To enable fast read access, the sensing of the stored data on the bit-line is typically accomplished using a sense amplifier which compares the current on the bit-line with a reference current. In conventional flash memory devices, the reference current is generated using a reference flash memory cell having the same construction as the flash memory cell in the memory array.
In some applications, a flash memory device may be configured to perform a serial read operation. For example, the flash memory device may be configured to perform a block read or a page read from the memory cell array. In that case, on the receipt of a read command and an initial memory cell address, the flash memory device automatically read out stored data from a block or a page of memory cells starting from the initial memory cell address. In a serial read operation, the memory cells in the block are assessed sequentially to read out the stored data. The flash memory device reads stored data from each memory cell using a ready cycle which starts at the assertion of the Address Transition Detection (ATD) signal on the detection and latching of a memory cell address and ends at the latching of the output data at the sense amplifier output. Then, the memory cell address is incremented and the next read cycle begins.
The speed of the read cycle is limited by the cell current and the loading on the bit-line. To access stored data from a flash memory cell, the selected bit-line is pre-charged and the selected word-line is biased up to the read target voltage. The selected bit-line and the reference bit-line are equalized and then the memory cell is sensed to read out the stored data. The most time consuming part of a read cycle is the time duration required to precharge and equalize the bit-line and the reference bit-line before sensing can take place.